ON SEMICONDUCTOR CORP

FOLLOW-ON SEMICONDUCTOR ANALYSIS, PROGRAM MANAGEMENT, AND CONTENT DEVELOPMENT SUPPORT

R&D RELATING TO NUCLEAR AND SPACE RADIATION EFFECTS ON SEMICONDUCTORS

THE GOAL OF THE CONTRACTOR S WORK IS TO DEVELOP SEVERAL NEW ULTRA-LOW LOSS HOLLOW-CORE WAVEGUIDES USING HIGH-CONTRAST GRATINGS ON SEMICONDUCTOR WAFERS AND DEVELOP HIGH EFFICIENCY COUPLERS AS WELL AS SPLITTER/COMBINERS FOR THE HOLLOW-CORE WAVEGUIDE SUCH THAT A CHIP SCALE OPTICAL DELAY CIRCUIT IS BUILD WITH A DEVICE LOSS THAT IS ORDER OF MAGNITUDE LOWER THAN THE CURRENT STATE-OF-THE-ART IN ON-CHIP SEMICONDUCTOR WAVEGUIDE.

THE GOAL OF THIS PROGRAM IS TO DEVELOP HIGH PERFORMANCE, HIGH SPEED, INTEGRATED OPTICAL SWITCHES FOR APPLICATIONS REQUIRING THE SWITCHING OF FOUR LASERS INTO ONE PM FIBER. THESE SWITCHES WILL BE OF SMALL SIZE AND WEIGHT GIVEN THAT THEY WILL BE FABRICATED AS A PHOTONIC INTEGRATED CIRCUIT (PIC) AND WILL BE DESIGNED TO MEET THE FOLLOWING TARGET SPECIFICATIONS: FOUR INPUT CHANNELS AND ONE OUTPUT CHANNEL CROSS-TALK BETWEEN CHANNELS BETTER THAN 30 DB NET OPTICAL GAIN THROUGH SWITCH SWITCHING SPEED<1 S SWITCHING RATE OF ~1-3 KHZ THE OPTICAL SWITCH WILL BE BASED ON SEMICONDUCTOR OPTICAL AMPLIFIERS (SOAS) AND A PASSIVE COMBINER. THE SOA HAS IN PREVIOUS DEMONSTRATIONS BEEN PROVEN TO MEET THE TARGET SPEED, GAIN AND CONTRAST REQUIREMENTS OF THIS EFFORT.

"IGF::OT::IGF" A MULTI-PIXEL DELTA-SIGMA MODULATED LASER DETECTION CIRCUIT REALIZED IN STANDARD COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) PRIMARY TASK THE CONTRACTOR SHALL DESIGN AND MANUFACTURE A DELTA-SIGMA MODULATION (DSM) BASED LASER DETECTION CIRCUIT BASED ON GOVERNMENT-FURNISHED DOCUMENTATION. THIS IS A MID-STAGE DEVELOPMENT EFFORT. THE CONTRACTOR SHALL FINALIZE THE MULTI-CHANNEL MANUFACTURING DESIGN BASED ON THE RESULTS OF PREVIOUS EFFORTS. THE AWARD IS FIXED-PRICE. LONG-TERM GOAL: TO DEVELOP A MULTI-CHANNEL LASER DETECTION CIRCUIT SUITABLE FOR LOW-INTENSITY OPTICAL SOURCES OPERATING IN EXTREME TEMPERATURE AND RADIATION ENVIRONMENTS. IN THE LONG-TERM, THIS DESIGN WILL BE PORTED TO A MORE SOPHISTICATED PROCESS. TO MEET LONG-TERM PROJECT GOALS, THE PREFERRED PARTNER WILL HAVE DEMONSTRABLE EXPERIENCE IN BOTH THE PRESENT DESIGN PROCESS (ON SEMICONDUCTOR C5 CMOS WITH HI-POLY RESISTORS AND DUAL-POLY CAPACITORS) AND THE PROJECTED FUTURE PROCESS (JAZZ SEMICONDUCTOR SBC18 OR SBC35 SIGE CMOS) STATEMENT OF WORK: THE EFFORT INVOLVES THE DEVELOPMENT OF A CMOS INTEGRATED CIRCUIT CONTAINING MULTIPLE COPIES OF THE PRIMARY NETWORK OF A SINGLE-PIXEL DELTA-SIGMA MODULATED LASER DETECTION CIRCUIT. THE GOAL OF THIS EFFORT IS TO DEMONSTRATE THE CAPABILITY OF MULTIPLE CHANNELS TO MEASURE INDEPENDENT SIGNALS WHILE SHARING COMMON ASPECTS OF THE NETWORK SUCH AS BIASING. THE DESIGN WILL BE BASED UPON GOVERNMENT-PROVIDED INFORMATION WITH MODIFICATIONS AS MUTUALLY AGREED UPON DURING THE COURSE OF DEVELOPMENT. THE PROJECT INVOLVES THE DESIGN, ANALYSIS, AND LAYOUT OF AN INTEGRATED CIRCUIT (IC) USING STANDARD CMOS PROCESS TECHNOLOGY. THE VENDOR SHALL PERFORM DESIGN, LAYOUT, SIMULATION, AND POST-MANUFACTURING TESTING OF PERFORMANCE MEASURES OF THE NETWORKS ON THE IC USING DESIGN TOOLS SUITABLE FOR INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT. SUCH TOOLS AT A MINIMUM SHALL INCLUDE CIRCUIT SIMULATION AT THE DEVICE LEVEL, DESIGN-RULE-CHECK (DRC), LAYOUT-VS-SCHEMATIC (LVS), AND PARASITIC EXTRACTION FROM LAYOUT. THESE ARE BASIC AND NECESSARY CAPABILITIES. ADDITIONAL SUB-NETWORKS MAY BE REQUIRED AS INDIVIDUAL TEST PLATFORMS; TYPE AND NUMBER TO BE DETERMINED AND DEFINED DURING DETAILED ANALYSIS PERFORMED BY THE CONTRACTOR. PROPOSALS FOR THE POTENTIAL SUB-NETWORKS ARE TO BE REVIEWED AND APPROVED BY THE GOVERNMENT. ADDITIONAL TESTING WILL BE PERFORMED AT NASA LANGLEY RESEARCH CENTER. THE CONTRACTOR SHALL PACKAGE THE TEST DIE IN STANDARD PLASTIC OR CERAMIC PACKAGES OF A SIZE TO BE DETERMINED AT THE MID-DESIGN REVIEW. THE CONTRACTOR SHALL PERFORM PRIMARY FUNCTIONAL TESTING OF DIE. AMONG THE BASIC TESTS WILL BE OPERATION AT NOMINAL SUPPLY VOLTAGE, NOMINAL SUPPLY CURRENT AT NOMINAL VOLTAGE, TEST-TO-DESTRUCTION OF SUPPLY VOLTAGE RANGE, OPERATION UNDER NOMINAL SUPPLY VOLTAGE RANGE, NOMINAL OUTPUT RESPONSE VS. INPUT STIMULUS, AND CHANNEL-TO-CHANNEL INTERACTION. OTHER TESTS MAY BE SUGGESTED DURING THE DEVELOPMENT PROCESS. THE CONTRACTOR SHALL DESIGN AND FABRICATE THE IC USING THE ON SEMICONDUCTOR C5 MANUFACTURING PROCESS. IT IS SUGGESTED BUT NOT REQUIRED THAT SUCH PROCESSING BE ORGANIZED THROUGH MOSIS TO MAINTAIN COMPATIBILITY WITH THE GOVERNMENT S EFFORTS ON THIS PROJECT. MILESTONES: 1.DESIGN, FABRICATE, AND TEST THE PROTOTYPE ICS BUILT UPON THE ON SEMICONDUCTOR C5 0.5&#61549;M PROCESS.DESIGN WILL BE READY FOR SUBMISSION TO FOUNDRY ON OR BEFORE THE DATES REQUIRED BY THE FOUNDRY BUTNO LATER THAN DEC 31, 20151. 2.COMPILATION OF TEST RESULTS SHALL INCLUDE CRITIQUE OF AS-TESTED DESIGN AND SUGGESTIONS FOR FUTUREDESIGN IMPROVEMENTS. DELIVERABLES: 1.PROJECTED CONTRACTOR SCHEDULE OF EVENTS AND DEVELOPMENT ACTIVITIES 2.PROGRESS REPORTS PRELIMINARY TO EACH NASA SITE PARTICIPATION. ANTICIPATED TIME FRAMES INCLUDE TBD (KICKOFF), TBD (MID-TERM DESIGN REVIEW), TBD (FINAL DESIGN REVIEW), TBD (TEST REVIEW MEETING) 3.DESIGN FILES FOR ALL NETWORK DESIGNS INCLUDING BUT NOT LIMITED TO: A.DESIGN ANALYSES, B.SIMULATION CIRCUITS AND MODEL LISTINGS, C.LAYOUT DESIGN

THIS PURCHASE IS FOR PERFORM ELECTRICAL AND OPTIC MEASUREMENTS AND ANALYSES ON SEMICONDUCTOR SAMPLES PROVIDED BY NAS AS PER QUOTE DATED 09/23/2021...PERIOD OF PERFORMANCE IS 10/01/2021 TO 09/30/2022.

CONDUCT OPTICAL MEASUREMENTS AND ANALYSIS ON SEMICONDUCTOR SAMPLES PROVIDE BY NASA

CONDUCT OPTIC MEASUREMENTS AND ANALYSES ON SEMICONDUCTOR SAMPLES PROVIDED BY NASA

PERFORM SYNCHROTRON WHITE BEAM X-RAY TOPOGRAPHY ON SEMICONDUCTOR SAMPLES PROVIDED BY NASA/MSFC

PERFORM SYNCHROTRON WHITE BEAM X-RAY TOPOGRAPHY ON SEMICONDUCTOR SAMPLES PROVIDED BY NASA/MSFC